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Description- Develop, improve and maintain various aspects of physical verification flow and methodology - Coordinate the effort of validating flows, improving for custom checks and data generation - Work with the design and PD teams to facilitate the chip design process - Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs - Collaborate with tool vendors and foundries for PDK performance enhancementsMinimum QualificationsPrevious industry experience in Silicon chip design flowsIP/SOC level PDV debug experience in various technology nodesScripting skills in programming languages such as Python, Perl, Tcl, Shell, Makefile or CExperience with flow automation and developmentMinimum requirement of BS and 3+ years of relevant industry experiencePreferred QualificationsKnowledge in Calibre/ICV/Pegasus runset coding for DRC/LVSRule coding in PERC is a plusKnowledge of parasitic extraction, SKILL coding, and PnR tools is a plusAdditional RequirementsMoreApple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
