Meta is hiring ASIC Power Engineers within our Infrastructure organization to work on power/performance optimizations from SOC Architecture to System level. We are looking for individuals with experience in power architecture definition and power management for large complex disaggregated ASICs, with exposure to power modeling, developing flows around EDA tools, and low-power design to build efficient System on Chip (SoC) and IP for data center applications.ASIC Engineer, Power Responsibilities:Work with Architecture and Design teams to assess power/performance tradeoffs at design/arch/process-tech levels and drive for solutions for Meta workloads.Define the power specification at system and module level for Idle, TDP, Typical use cases.Develop power modeling infrastructure in Python/C++.Work with or develop architectural simulators in order to model performance and power.Build power estimation flows at various levels of abstraction: C-model, RTL, Gate, Layout.Optimize design for low-power with the understanding of system level concepts Evaluation and Implementation of low-power design techniques at different levels of abstraction.Power characterization on silicon: idle, TDP, use case power & debug power issues on silicon.Partner with vendors to drive low-power requirements for SoC interfaces such as LPDDR, PCIe, etc..Partner with EDA tool vendors to select and deploy the appropriate power estimation tools.Collaborate with internal HW/SW Co-design, Architecture, Design, DV, and Emulation teams for power flows, optimization and estimation.Minimum Qualifications:
Meta is hiring ASIC Power Engineers within our Infrastructure organization to work on power/performance optimizations from SOC Architecture to System level. We are looking for individuals with experience in power architecture definition and power management for large complex disaggregated ASICs, with exposure to power modeling, developing flows around EDA tools, and low-power design to build efficient System on Chip (SoC) and IP for data center applications.ASIC Engineer, Power Responsibilities:
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