ASIC Design for Testability Engineer, Silicon

Minimum qualifications:Bachelor’s degree in Computer Science, Electronics or Electrical Engineering, or equivalent practical experience.5 years of experience in ASIC design for test including complete silicon life cycle through DFT pattern bring-up on ATE and manufacturing.Experience with ATPG, Low Power designs, BIST, JTAG, IJTAG tools and flow.Experience with DFT EDA tools (e.g., Tessent).Preferred qualifications:Experience with scripting languages such as as Perl or Python.Experience in DFT for a Complex subsystem with multiple physical partitions.Knowledge of high performance design DFT techniques like SSN, HighBandwidth IJTAG.Understanding of the flows - Design, Verification, DFT and PD Phases in a SOC cycle.Ability to scale DFT, with a focus on minimal area overhead.

Minimum qualifications:

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